The present invention generally relates to integrated circuits and to more specifically to yield testing of local interconnects.
Integrated circuits becomes smaller and smaller as technology allows device sizes to shrink. The quality of the dielectric and the control of local interconnects (LI) are key points for the reliability size reduction of integrated circuits.
Presently, local interconnect continuity is monitored during manufacturing through continuity measurements at a few locations on a few wafers of each lot. More specifically, yield testing or macro design for lithography process monitoring is an important to monitor to “local interconnect contact B” (LIB) landing on gate continuity and “Local interconnect contact A” (LIA) landing on source/drain region.
Previous yield testing processes or macro, such as “polycrystalline gate” (PC) LIB open macro, failure analysis has shown that LIB pattern defects are a major cause of low yield. The prior art PC LIB macro was also impacted by PC continuity which makes it impossible to decouple the PC continuity defects and the LIB continuity defects.